Xilinx and Huawei demonstrated a prototype 400 Gb/s Ethernet interface at the Optical Fiber Conference, which took place March 9-13, 2014, in the Moscone Center in San Francisco.
The 400 Gb/s Ethernet IEEE task force is still in the process of being created to work on the new standard, so this prototype does not conform to any IEEE spec. The Huawei-Xilinx interface is based on 16 PCS (Physical Coding Sublayer) lanes operating at 25 Gb/s each, but they state that other configurations are possible depending on how the standards process works out.
This Xilinx blog posting notes that the interface is based on a pair of Xilinx FPGAs (field-programmable gate arrays) that are in volume production, based on a 28-nanometer manufacturing process. A planned upgrade of the FPGA will be based on a single chip manufactured with a 20nm process, which reduces the space and power required for the transceiver electronics.
The interface, which was demonstrated in the Huawei NetEngine NE5000E cluster router, provides connections to four 100 Gb/s CFP2 optical modules. This makes it possible to transmit a total of 16 PCS lanes operating at 25 Gb/s each over 400 Gb/s of media bandwidth.